Espressif Systems /ESP32-P4 /H264_DMA /INFIFO_STATUS_CH1

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Interpret as INFIFO_STATUS_CH1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INFIFO_FULL_L2_CH1)INFIFO_FULL_L2_CH1 0 (INFIFO_EMPTY_L2_CH1)INFIFO_EMPTY_L2_CH1 0INFIFO_CNT_L2_CH1 0 (INFIFO_FULL_L1_CH1)INFIFO_FULL_L1_CH1 0 (INFIFO_EMPTY_L1_CH1)INFIFO_EMPTY_L1_CH1 0INFIFO_CNT_L1_CH1 0 (INFIFO_FULL_L3_CH1)INFIFO_FULL_L3_CH1 0 (INFIFO_EMPTY_L3_CH1)INFIFO_EMPTY_L3_CH1 0INFIFO_CNT_L3_CH1

Description

RX CH1 INFIFO status register

Fields

INFIFO_FULL_L2_CH1

Rx FIFO full signal for Rx channel.

INFIFO_EMPTY_L2_CH1

Rx FIFO empty signal for Rx channel.

INFIFO_CNT_L2_CH1

The register stores the byte number of the data in Rx FIFO for Rx channel.

INFIFO_FULL_L1_CH1

Tx FIFO full signal for Tx channel 1.

INFIFO_EMPTY_L1_CH1

Tx FIFO empty signal for Tx channel 1.

INFIFO_CNT_L1_CH1

The register stores the byte number of the data in Tx FIFO for Tx channel 1.

INFIFO_FULL_L3_CH1

Tx FIFO full signal for Tx channel 1.

INFIFO_EMPTY_L3_CH1

Tx FIFO empty signal for Tx channel 1.

INFIFO_CNT_L3_CH1

The register stores the byte number of the data in Tx FIFO for Tx channel 1.

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